This invention relates generally to sense amplifiers as used in reading and sensing data stored in memory arrays, and more particularly the invention relates to load devices for such amplifiers which allow faster data access times.
A sense amplifier is employed in reading data stored in a memory array. In a fast Erasable Programmable read only memory (EPROM), data (D) and the complement of data (D) are stored in two adjacent memory transistors which are addressable by word lines (x address) and bit lines (y address). When a cell is addressed for data access, the stored datum and its complement are connected to the sense amplifier through selected gates. The data are sensed as either a voltage or a current.
In a CMOS current sense amplifier a diode-connected PMOS transistor often functions as a loading device (current mirror) in sensing the current. However, this load device often delays the sensing of current since when the output node voltage goes down, the conductivity of the load device goes higher and the fall time of the output node is delayed. Conversely, when a selected memory cell is not conducting, the load device pulls up the output node. However, as the output node goes up in voltage, the conductivity of the load device goes lower and the rise time of the output node is slowed.
The present invention is directed to a load device for a sense amplifier in which load conductivity is low when the output goes down and is high when the output goes up.